1. Field of the Invention
The present invention relates to computer hardware design and in particular to a printed circuit board comprising wiring dedicated to supply electric board components such as integrated circuits with at least three different reference planes.
2. Description and Disadvantages of Prior Art
Those reference planes are metallization planes which implement often one ground and two different voltage levels, often denoted as GROUND, Vdd and V3, thus e.g. GND=0 Volt, Vdd=1.8 Volt, and for example an intermediate voltage level V3 as e.g., V3=1.5 Volt. Those printed circuit boards comprise an interface circuit, a single chip module, or a multiple chip module between board and a component, wherein said interface circuit in turn comprises vias for signal wiring and for the supply voltages.
It is useful to differentiate between different packaging levels, where different electrical situations prevail, but which must be electrically connected to each other for operation. Such packaging levels are for instance (in a bottom up view): The chip as a zero packaging level, chip-module as a first packaging level, cards (so called printed wiring boards) carrying different single chip-modules or multiple chip-modules as a second packaging level, or so called mother boards carrying different card connectors with daughter cards as a third level package.
In printed circuit boards of complex computer systems a lot of performance critical high-frequency signals do not stay within one packaging level not even on one card.
With reference to FIG. 1 a card 110 is depicted with a chip module 112 mounted thereon, which in turn acts as a carrier for a chip 114. The high frequency signals often pass the before-mentioned different packaging levels and components like Chip level, Single Chip Modules (SCM) or Multi Chip Modules (MCM), SCM or MCM connectors, card levels, card connectors, back plane boards, etc.
In each of the packaging levels and components signals are referenced to voltage and ground layers, pins or Plated Through Holes (PTH's) adjacent to them. In some applications as depicted in FIG. 1, up to 3 or 4 different voltages V1, V2, and V3 (Ground, and some supply voltages) need to be connected between printed circuit board also referred to herein as “card”, and the chip and thus also to the SCM and MCM used in-between. This is schematically depicted in FIG. 1.
With special focus to the present invention high speed digital signals cross the packaging levels in crossing parts, like interconnection vias, or in other structures like bond wires, solder balls, connectors. With increase of digital signal bus speed and fast rise time signal, some small discontinuities like via and non-normal return path on a bus are becoming more important factors for signal quality and timing.
To close the signal return path between a SCM/MCM connector 111 and the card is a special challenge. Usually the signals in the card are referenced to ground (GND) and one of the voltage levels, e.g. voltage 1. If the signal is approaching the module connector the reference can change depending on the voltage and/or ground pin 116 adjacent next to the signal pin 115. In a worst case situation the signal is referenced in the module 112 to just one other voltage, e.g. voltage V2, which is different to the card internal reference plane for this signal. In this case the high frequency signal return path is totally broken. Due to these discontinuities signal coupling will increase dramatically for high frequency signals or signals with a steep signal slope. In order to close the high frequency signal return path and thus limit the signal coupling, a straight forward approach could contain to modify the card cross sections in an appropriate way.
In order to obtain a high-quality signal, an impedance variation should be kept as small as possible in those crossing parts in order to keep the signal distortion as small as possible. Also the discontinuity of the signal return path plays a major role to obtain this goal. The more a return path of the high frequency signal is closed the better is the signal quality. Discrete capacitors mounted on the card surface are not effective for closing the return path due to the large parasitic via inductance. In addition, the high frequency return current is caused by the electromagnetic field surrounding the signal wire. Thus the high frequency return current is directly associated with the electromagnetic field and the signal current. At a discontinuity the electromagnetic field is directly jumping from one reference to the next e.g. power or ground (GND) plane to the module connector plated through hole abbreviated herein as PTH. If there are more signal than power PTHs or ground PTHs, signal coupling will be increased.
With further reference to a publication in IBM Journal of Research and Development, Vol. 48, No. 3/4, published May, July 2004 and FIGS. 2, 3, 4 and 5 (table representation) three exemplary cases of a card-to-card connections are given having different electrical properties in terms of the before-mentioned high-frequency crosstalk problems. In the above publication the technological background for this problem is discussed.
In order to demonstrate the effects of non ideal high frequency signal return path measurements were performed by the authors of above publication on a special card test vehicle (two cards connected with a card connector).
FIG. 2 is a partly cross-sectional view including a multi layer structure illustrating a signal wiring from a more top layer to a more bottom layer, crossing the intermediate layers by a via, illustrating the schematics of the electro-magnetic field around the signal wiring and the associated high frequency signal return path in the layers adjacent to the signal wire, in an ideal case, wherein the signal wiring is embedded always between two power planes or two ground planes. Here the return path is basically closed all over the signal travel from card 1, over the via of the connector, until reaching card 2, as the signal is embedded always with the same voltage reference (either Ground, or Power).
FIG. 3 is a depiction according to FIG. 2 including a voltage plane separating signal line 35 and an additional signal plane 36 in the card 2 portion.
In the top portion of card 1 the same good closing of the return path is achieved.
In the bottom portion of card 2 however the signal 36 is embedded between a ground plane 20 and a voltage plane 30. This implies a return path which is slightly worse than in FIG. 2.
FIG. 4 is a depiction according to FIG. 3 illustrating a “worst” case high frequency signal return path including a floating pin 40. Floating can be assumed to occur due to the fact that pin 40 is connected to a reference voltage or to Ground in a quite long distance only. From this floating state a high noise coupling results from signal line 36 to signal line 36. The exact results are given in the table of FIG. 5.
Measurements performed for the case 2 prove that the high frequency return is nearly as good as for the ideal case 1.
In contrast to that measurements performed for the case 3 show a significant increase of coupled noise. In case 3 the floating pin is not connected to any reference plane in card 1 or 2. Therefore the high frequency return current in all other adjacent pins will be increased and thus signal coupling will be increased if the next neighbouring pins are signal pins. In table 1 the near and far end coupling is depicted for all three cases. Near end coupling is to be understood as the coupling which is seen at the launching device, the so called driver circuit in the upper portion of the drawing, and far end coupling as that one that is seen at the receiving device, the so called receiver circuit in the bottom part. In comparison, while the differences in coupling in case 1 and 2 are negligible, the coupling increases significantly in case 3 by a factor of 4 (near end) and 10 . . . 11 for the far end. Usually a floating pin 40 is not used in the system design. From a high frequency return path of view, a module connector pin connected to a voltage or ground plane far away from the internal signal wire connected to the signal pin behaves like a floating pin. This means with increasing distance of the pin (carrying the high frequency return signal) to the power/ground connection, the signal coupling will also increase.
A further printed circuit board structure is disclosed in a product sold by IBM, available under IBM eServer zSeries z990 product family. It discloses the technical context illustrated in FIGS. 6 and 7. In this disclosure soft switches are mentioned which are used to prevent cards from being damaged by an “over-current”. The soft switch separates the card 1 internal voltage 2, FIG. 6, from the source voltage 1 in card 2. The high frequency return path of the signal path, when passing from card 1 to card 2, is said to be broken, which would result in an increased signal coupling. In order to limit the signal coupling it is disclosed to add a second voltage plane as shown in prior art FIG. 7. Thus, a complete plane pair exists having a level of voltage 1 and voltage 2, respectively which is said to limit the impedance mismatch and the signal-to-signal coupling at the card discontinuity and to provide a good high frequency signal return path due to an efficient internal plane capacitance.
This solution is, however, not applicable for cost-driven card designs as the additional plane increases the costs.
Thus keeping in mind the before-mentioned technical problems of signal crosstalk in high frequency digital signals across the different packaging levels, reference will now be made to FIG. 8, which is a prior art, schematic cross-section representation illustrating the single layers in a printed circuit board 110 according to FIG. 1. In FIG. 8 a layer will be identified by reference to its individual layer number, denoted at the right margin of the drawing.
The layer structure given in FIG. 8 is disclosed in the IBM eServer zSeries z9.
In FIG. 8, layers 1 to 16 are depicted. Layer 1 is a mounting plane for mounting electrical components like card-to-card connectors, card to SCM/MCM connectors, SCMs, chip packages and other passive and active electrical components. Under the mounting plane no. 1 connecting from card to e.g. the SCM connector, a layer no. 2 is provided carrying a voltage level V1. This can be a supply voltage of e.g. 1.5 Volt. Beneath that layer a signal layer no. 3 is provided. Beneath layer no. 3, a ground layer no. 4 is located. Then a second signal layer, layer no. 5 is provided followed by a second voltage layer, V2 as layer no. 6. Beneath layer 6 a third signal layer is provided followed by a ground layer, layer no. 8.
Then the same layer sequence is repeated in an inverse manner in order to make the total layer sequence symmetrical to the line defined by both ground layers no. 8, and no. 9. The layer structure ends with the bottom layer 16 which is again a mounting plane for mounting the structure to electrical components like card-to-card connectors, card-to-SCM/MCM connectors, SCMs, chip packages and other passive and active electrical components.
The disadvantage of this layer stack up is that the signals in layers 3, 5, 7, 10, 12, 14 just have dedicated references adjacent to the signal lines. Signals in signal layer 3 are just referenced to V1 and GND, signals in layers 5 and 7 are just referenced to V2 and GND, signals in layer 10 and 12 are just referenced to V3 and GND and signals in layer 14 are just referenced to V4 and GND. If the signals are wired to other electrical components mounted on the card having a different voltage adjacent to the signals and thus a different reference, the high frequency return path is broken causing higher signal crosstalk.
In order to close the high frequency signal return path in the card 10, one would basically need to have at least one signal layer adjacent to each voltage and to GND. This, however, is not a practical solution, because the fan-out of the signal wires in the module area need to be very well controlled which is very time-consuming and therefore expensive. In addition, just one signal layer referenced to one of the voltages might not be enough to fan out all signals. Adding more signal layers with the appropriate voltage reference would however blow up the cross section thickness which increases the costs. Cost-driven card and system designs thus need special design solutions in order to find a well performing design having offering an acceptable trade-off between cost and the optimum electrical design.